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the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all devices/types available in every country. please check with local nec representative for availability and additional information. ? 1998, 1999 mos integrated circuit m m m m pd16664 144/160/184/208-output lcd column (segment) driver with ram data sheet document no. s13780ej1v0ds00(1st edition) date published september 1999 ns cp(k) printed in japan the mark ? ? ? ? shows major revised points. description the m pd16664 is a column (segment) driver with internal ram and can drive a full-dot lcd. equipped with 144/160/184/208-output pins and a display ram of 208 x 160 x 2 bits, this driver can display any of four gray levels selected from a 25-level palette. by using this ic in combination with the m pd16667, 144 x 128 pixels to 416 x 320 pixels can be displayed. features internal display ram : 208 x 160 x 2 bits logic voltage : 2.4 to 3.6 v duty : 1/128, 1/160 selectable number of outputs : 144,160,184 and 208 pins selectable display : four gray levels (selectable from 25-level palette) memory management : packed pixel method supports 8/16-bit data bus ordering information part number package m pd16664n-xxx tcp (tab) m pd16664n-001 2/4-side standard tcp remark the tcps external shape is customized. to order the required shape, please contact an nec salesperson.
data sheet s13780ej1v0ds00 2 m m m m pd16664 1. pin name classification pin name note i/o function cpu interface v cc2 d 0 -d 15 a 0 -a 16 /cs /oe /we /ube rdy i/o i i i i i o data bus: 16 bits address bus: 17 bits chip select read signal write signal upper byte enable ready signal to cpu (h: ready) control signals v cc2 pl0 pl1 dir dmode cmode0,1 ms bmode /refrh test /reset /doff osc1 osc2 i i i i i i i i/o i i i C C specifies lsi layout position (no. 0 to 3) specifies lsi layout position (no. 0 to 3) specifies liquid crystal panel layout position duty selection (h = 1/128 duty, l =1/160 duty) number of column outputs selection master/slave selection (h: master mode) data bus bit selection (h = 8 bits, l = 16 bits) self-diagnosis reset pin (wired-or connection) test pin (h = test mode, with pull-down resistor) reset signal display off input signal external resistor pin for oscillator external resistor pin for oscillator v cc1 stb /frm pulse l1 l2 /dout i/o i/o i/o i/o i/o o column drive signal (ms pin h = output, ms pin l = input) frame signal (ms pin h = output, ms pin l = input) 25-level pulse modulation clock row driver drive level select signal (first line) row driver drive level select signal (second line) display off output signal liquid crystal drive y 1 -y 208 o liquid crystal drive output power gnd v cc1 v cc2 v 0 v 1 v 2 C C C C C C ground (two pins for v cc1 system, three pins for v cc2 system) power supply for liquid crystal drive and row driver interface power supply for logic liquid crystal drive analog power liquid crystal drive analog power liquid crystal drive analog power note v cc2 system pins : d 0 to d 15 , a 0 to a 16 , /cs, /oe, /we, /ube, rdy, bmode, pl0, pl1, dir, osc1, osc2, /reset, /doff, test, ms, cmode0, cmode1, dmode v cc1 system pins : stb, /frm, l1, l2, /dout, pulse remark /xxx indicates active low si gnals.
data sheet s13780ej1v0ds00 3 m m m m pd16664 2. block diagram dir pl0, 1 test a 0 -a 16 control /cs, /oe /we, /ube d 0 -d 15 /refrh /reset /doff v cc2 operation v cc1 operation ms osc1 stop osc2 rdy bmode v cc2 operation v cc1 operation address input control address management circuit arbiter ram 208 160 2 bits data latch (1) data latch (2) gray level generation circuit internal timing generation self-diagnosis circuit gray level control data bus control cr oscillator liquid crystal timing generation pulse pulse /frm /frm stb stb /dout l1 l2 y 1 y 2 y 3 v 0 v 1 v 2 y 208 liquid crystal drive circuit 208 outputs dec level shifter cmode0,1 dmode
data sheet s13780ej1v0ds00 4 m m m m pd16664 3. block function (1) address management circuit this circuit converts addresses from the system via a 0 to a 16 into addresses corresponding to the memory map of the internal ram. by using this function and four m pd16664 modules, addresses for up to 416 320 pixels can be managed, making it easy to construct a liquid crystal display system. addresses 1ff00h to 1ff1eh are allocated to a gray level palette register, and any four gray levels can be selected from a 25-level palette. (2) arbiter this circuit arbitrates conflicts between access by the system to the ram and reading the ram by the lcd driver. (3) ram this is a static ram of 208 x 160 x 2 bits (single port). (4) data bus control this circuit controls the data transfer direction depending on whether the system reads or writes the ram of the m pd16664. the data bus width can be changed between 8 and 16 bits by the bmode pin. (5) gray level generation circuit this circuit offers 25 levels by means of frame interpolation and pulse width modulation. (6) internal timing generation this circuit generates internal timing signals for each block from the /frm and stb signals. (7) cr oscillator this oscillator generates a clock that serves as the reference of the frame frequency in the master mode. because this cr oscillator has an on-chip capacitor, the necessary oscillation frequency can be adjusted by using an external resistor. oscillation is stopped in the slave mode. (a) 1/160 duty the frame frequency is 1/1296 of the oscillation frequency of this oscillator. for example, when the frame frequency is 70 hz, the oscillation frequency is 90.72 khz. (b) 1/128 duty the frame frequency is 1/1040 of the oscillation frequency of this oscillator. for example, when the frame frequency is 70 hz, the oscillation frequency is 72.80 khz. (8) liquid crystal timing generation this circuit generates the /frm (frame signal), stb(column drive signal strobe), and pulse (25-level pulse modulation clock) signals in the master mode.
data sheet s13780ej1v0ds00 5 m m m m pd16664 (9) gray level control this circuit implements the 4-gray level display. (10) data latch (1) this circuit reads data for 208 pixels from ram and latches it. (11) data latch (2) this circuit latches data for 208 pixels in synchronization with the stb signal. (12) level shifter the level shifter converts the operating voltage of the internal circuit(v cc2 ) into the voltage for the liquid crystal driver circuit and row driver interface (v cc1 ). (13) dec this is a decoder that decodes gray level display data to liquid crystal drive voltages v 0 , v 1 , or v 2 . (14) liquid crystal drive circuit this circuit selects liquid crystal drive voltage v 0 , v 1 , or v 2 corresponding to gray level display data and the display off signal (/doff), to generate a liquid crystal application voltage. (15) self-diagnosis circuit if the operation timing of the master chip and that of the slave chip differ due to external noise, this circuit automatically detects the difference and generates a refresh signal to all column drivers.
data sheet s13780ej1v0ds00 6 m m m m pd16664 address map image (cmode0 = l, cmode1 = l, dmode = l) a 7 through a 0 specify column direction. a 16 through a 8 specify line direction. y 1 y 1 y 1 y 1 y 208 y 208 y 208 l160 l160 l1 l1 y 208 no. 0 no. 2 no. 1 no. 3 address incrementing direction address incrementing direction
data sheet s13780ej1v0ds00 7 m m m m pd16664 4. data bus the byte data ordering on the data bus is little endian, in common with most nec and intel buses. 4.1 16-bit data bus (bmode = l) byte access d 0 to d 7 d 8 to d 15 address incrementing direction 00000h 00002h 00004h : : 00001h 00003h 00005h : : word access d 0 to d 7 d 8 to d 15 address incrementing direction 00000h 00002h 00004h : : if the system accesses the m pd16664 in word(16-bit) or byte(8-bit) units, /ube (upper byte enable) and a 0 specify whether bytes d 0 to d 7 or bytes d 8 to d 15 have valid data. /cs /oe /we /ube a 0 mode i/o d 0 to d 7 d 8 to d 15 h x x x x not selected hi-z hi-z llhl l h l h l read dout hi-z dout dout dout hi-z lhl l l h l h l write din x din din din x l l h x h x x h x h output disable hi-z hi-z hi-z hi-z remark x : dont care hi-z : high impedance
data sheet s13780ej1v0ds00 8 m m m m pd16664 4.2 8-bit data bus (bmode = h) d 0 to d 7 address incrementing direction 00000h 00001h 00002h : : /cs /oe /we mode i/o d 0 to d 7 d 8 to d 15 h x x not selected hi-z note l l h read dout note lhlwrite din note l h h output disable hi-z note note leave d 8 to d 15 open because they are internally pulled down. remark x: dont care hi-z: high impedance
data sheet s13780ej1v0ds00 9 m m m m pd16664 5. relation between data bits and pixels because the m pd16664 displays four gray levels, 1 pixel consists of 2 bits. the ram consists of 4 pixels (8 pixels per word) using the packed pixel method. (1) bmode = l byte (8-bit) access d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 8 d 9 d 10 d 11 d 12 d 13 d 14 d 15 pixel 1 pixel 2 pixel 3 pixel 4 pixel 5 pixel 6 pixel 7 pixel 8 00000h 00001h liquid crystal panel pixel 1 pixel 2 pixel 3 pixel 4 pixel 5 pixel 6 pixel 7 pixel 8 pixel 1 pixel 2 pixel 3 pixel 4 pixel 5 pixel 6 pixel 7 pixel 8 00000h 00001h 00002h 00003h word (16-bit) access d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 8 d 9 d 10 d 11 d 12 d 13 d 14 d 15 pixel 1 pixel 2 pixel 3 pixel 4 pixel 5 pixel 6 pixel 7 pixel 8 00000h liquid crystal panel pixel 1 pixel 2 pixel 3 pixel 4 pixel 5 pixel 6 pixel 7 pixel 8 pixel 1 pixel 2 pixel 3 pixel 4 pixel 5 pixel 6 pixel 7 pixel 8 00000h 00002h (2) bmode = h d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 pixel 1 pixel 2 pixel 3 pixel 4 pixel 5 pixel 6 pixel 7 pixel 8 00000h 00002h liquid crystal panel pixel 1 pixel 2 pixel 3 pixel 4 pixel 5 pixel 6 pixel 7 pixel 8 pixel 1 pixel 2 pixel 3 pixel 4 pixel 5 pixel 6 pixel 7 pixel 8 00000h 00001h 00002h 00003h
data sheet s13780ej1v0ds00 10 m m m m pd16664 6. gray level control the gray level control of the m pd16664 offers a 25-level palette by means of frame interpolation and pulse width modulation. from this palette, four gray levels are selected and registered in a gray level palette register. 7. gray level palette register the gray level palette register selects four gray levels from 25 levels in advance. this register is allocated to 1ff00h to 1ff1eh, and its relation with gray level data is as shown below. the gray level palette register can be set for each layout position of the column driver (no. 0 to 3) that is determined by pl0 and pl1. address layout position no. gray level data (display data) dn+1 note dn note 1ff00h 0 0 1ff02h no.0 0 1 1ff04h 1 0 1ff06h 1 1 1ff08h 0 0 1ff0ah no.1 0 1 1ff0ch 1 0 1ff0eh 1 1 1ff10h 0 0 1ff12h no.2 0 1 1ff14h 1 0 1ff16h 1 1 1ff18h 0 0 1ff1ah no.3 0 1 1ff1ch 1 0 1ff1eh 1 1 note n = 0, 2, 4, 6, 8, 10, 12, or 14
data sheet s13780ej1v0ds00 11 m m m m pd16664 8. relation between gray levels and gray level palette data the relation between the gray levels and the gray level palette data set by the gray level palette register is as follows: pmode gray level palette data remark d 4 d 3 d 2 d 1 d 0 gray level 000000 off gray level 100001 gray level 200010 gray level 300011 gray level 400100 gray level 500101 gray level 600110 gray level 700111 gray level 801000 1/3 gray level 901001 gray level 1001010 gray level 1101011 gray level 1201100 gray level 1301101 gray level 1401110 gray level 1501111 gray level 16 1 0 0 0 0 2/3 gray level 1710001 gray level 1810010 gray level 1910011 gray level 2010100 gray level 2110101 gray level 2210110 gray level 2310111 gray level 2411000 on
data sheet s13780ej1v0ds00 12 m m m m pd16664 9. lsi layout and address management addresses are managed so that up to four m pd16664s can be used to organize a liquid crystal display of 416 x 320 pixels. four modules can be connected on the same bus with the /cs, /we, and /oe pins shared. the system can treats one screenful of the liquid crystal display as one memory area, and does not have to decode more than one lsi. specify an lsi no. by using the pl0 and pl1 pin to determine the layout of the lsis, and determine the direction (vertical or horizontal) of the liquid crystal display by using the dir pin. pl1 pl0 lsi no. 0 0 1 1 0 1 0 1 no. 0 no. 1 no. 2 no. 3 10. number of column outputs selection cmode1 cmode0 number of column outputs valid pins 0 0 1 1 0 1 0 1 208 184 160 144 y 1 to y 208 y 1 to y 184 y 1 to y 160 y 1 to y 144 remark invalid column outputs are fastened to v 1 level. 11. duty selection dmode duty 0 1 1/160 1/128 note note valid row outputs of m pd16667 are x 1 to x 128 . invalid row outputs are undefined.
data sheet s13780ej1v0ds00 13 m m m m pd16664 horizontally long address dir = l, dmode = l 144-output mode no. 0 00022 00100 00020 00122 09e00 09f02 09e22 09f22 no. 1 13e00 13f00 0a022 0a122 13f02 13e22 13f22 no. 2 00024 00124 00046 00146 09e24 09f24 09e46 09f46 no. 3 0a024 0a124 0a046 0a146 13e24 13f24 13e46 13f46 y 144 y 144 y 1 y 1 y 144 y 144 y 1 x 160 x 1 x 160 00044 00026 09f44 09f26 00002 00000 09f00 09f20 0a020 13f20 0a044 0a026 13f44 13f26 0a100 0a002 0a000 x 1 y 1 pd16664 pd16664 pd16664 pd16664 pd16667 pd16667 m m m m m m specified by a 7 to a 0 specified by a 16 to a 8 160-output mode no. 0 00026 00100 00024 00126 09e00 09f02 09e26 09f26 no. 1 13e00 13f00 0a026 0a126 13f02 13e26 13f26 no. 2 00028 00128 0004e 0014e 09e28 09f28 09e4e 09f4e no. 3 0a028 0a128 0a04e 0a14e 13e28 13f28 13e4e 13f4e y 160 y 160 y 1 y 1 y 160 y 160 y 1 x 160 x 1 x 160 0004c 0002a 09f4c 09f2a 00002 00000 09f00 09f24 0a024 13f24 0a04c 0a02a 13f4c 13f2a 0a100 0a002 0a000 x 1 pd16667 pd16667 y 1 pd16664 pd16664 pd16664 pd16664 m m m m m m specified by a 7 to a 0 specified by a 16 to a 8 ?
data sheet s13780ej1v0ds00 14 m m m m pd16664 184-output mode no. 0 0002c 00100 0002a 0012c 09e00 09f02 09e2c 09f2c no. 1 13e00 13f00 0a02c 0a12c 13f02 13e2c 13f2c no. 2 0002e 0012e 0005a 0015a 09e2e 09f2e 09e5a 09f5a no. 3 0a02e 0a12e 0a05a 0a15a 13e2e 13f2e 13e5a 13f5a y 184 y 184 y 1 y 1 y 184 y 184 y 1 x 160 x 1 x 160 00058 00030 09f58 09f30 00002 00000 09f00 09f2a 0a02a 13f2a 0a058 0a030 13f58 13f30 0a100 0a002 0a000 x 1 y 1 pd16664 pd16664 pd16664 pd16664 pd16667 pd16667 m m m m m m specified by a 7 to a 0 specified by a 16 to a 8 208-output mode no. 0 00032 00100 00030 00132 09e00 09f02 09e32 09f32 no. 1 13e00 13f00 0a032 0a132 13f02 13e32 13f32 no. 2 00034 00134 00066 00166 09e34 09f34 09e66 09f66 no. 3 0a034 0a134 0a066 0a166 13e34 13f34 13e66 13f66 y 208 y 208 y 1 y 1 y 208 y 208 y 1 x 160 x 1 x 160 00064 00036 09f64 09f36 00002 00000 09f00 09f30 0a030 13f30 0a064 0a036 13f64 13f36 0a100 0a002 0a000 x 1 y 1 pd16664 pd16664 pd16664 pd16664 pd16667 pd16667 m m m m m m specified by a 7 to a 0 specified by a 16 to a 8
data sheet s13780ej1v0ds00 15 m m m m pd16664 vertically long address dir = h, dmode = l 144-output mode no. 0 00000 00100 00022 00122 09e00 09f00 09e22 09f22 no. 1 0a000 0a100 0a022 0a122 13e00 13f00 13e22 13f22 no. 2 00024 00124 00046 00146 09e24 09f24 09e46 0a046 no. 3 0a024 0a124 09f46 0a146 13e24 13f24 13e46 13f46 13f02 13f20 13f26 13f44 0a044 0a026 09f26 09f44 09f20 0a020 0a002 09f02 00002 00020 00026 00044 pd16667 pd16667 x 160 x 1 x 160 x 1 y 1 y 144 y 1 y 144 pd16664 pd16664 pd16664 pd16664 y 144 y 1 y 144 y 1 m m m m m m specified by a 16 to a 8 specified by a 7 to a 0 ?
data sheet s13780ej1v0ds00 16 m m m m pd16664 160-output mode no. 0 00000 00100 00026 00126 09e00 09f00 09e26 09f26 no. 1 0a000 0a100 0a026 0a126 13e00 13f00 13e26 13f26 no. 2 00028 00128 0004e 0014e 09e28 09f28 09e4e 0a04e no. 3 0a028 0a128 09f4e 0a14e 13e28 13f28 13e4e 13f4e 13f02 13f24 13f2a 13f4c 0a04c 0a02a 09f2a 09f4c 09f24 0a024 0a002 09f02 00002 00024 0002a 0004c pd16667 pd16667 x 160 x 1 x 160 x 1 y 1 y 160 y 1 y 160 pd16664 pd16664 pd16664 pd16664 y 160 y 1 y 160 y 1 m m m m m m specified by a 16 to a 8 specified by a 7 to a 0
data sheet s13780ej1v0ds00 17 m m m m pd16664 184-output mode no. 0 00000 00100 0002c 0012c 09e00 09f00 09e2c 09f2c no. 1 0a000 0a100 0a02c 0a12c 13e00 13f00 13e2c 13f2c no. 2 0002e 0012e 0005a 0015a 09e2e 09f2e 09e5a 0a05a no. 3 0a02e 0a12e 09f5a 0a15a 13e2e 13f2e 13e5a 13f5a 13f02 13f2a 13f30 13f58 0a058 0a030 09f30 09f58 09f2a 0a02a 0a002 09f02 00002 0002a 00030 00058 pd16667 pd16667 x 160 x 1 x 160 x 1 y 1 y 184 y 1 y 184 pd16664 pd16664 pd16664 pd16664 y 184 y 1 y 184 y 1 m m m m m m specified by a 16 to a 8 specified by a 7 to a 0
data sheet s13780ej1v0ds00 18 m m m m pd16664 208-output mode no. 0 00000 00100 00032 00132 09e00 09f00 09e32 09f32 no. 1 0a000 0a100 0a032 0a132 13e00 13f00 13e32 13f32 no. 2 00034 00134 00066 00166 09e34 09f34 09e66 0a066 no. 3 0a034 0a134 09f66 0a166 13e34 13f34 13e66 13f66 13f02 13f30 13f36 13f64 0a064 0a036 09f36 09f64 09f30 0a030 0a002 09f02 00002 00030 00036 00064 pd16667 pd16667 x 160 x 1 x 160 x 1 y 1 y 208 y 1 y 208 pd16664 pd16664 pd16664 pd16664 y 208 y 1 y 208 y 1 m m m m m m specified by a 16 to a 8 specified by a 7 to a 0
data sheet s13780ej1v0ds00 19 m m m m pd16664 horizontally long address dir = l, dmode = h 144-output mode no. 0 00022 00100 00020 00122 07e00 07f02 07e22 07f22 no. 1 0fe00 0ff00 08022 08122 0ff02 0fe22 0ff22 no. 2 00024 00124 00046 00146 07e24 07f24 07e46 07f46 no. 3 08024 08124 08046 08146 0fe24 0ff24 0fe46 0ff46 y 144 y 144 y 1 y 1 y 144 y 144 y 1 x 128 x 1 x 128 00044 00026 07f44 07f26 00002 00000 07f00 07f20 08020 0ff20 08044 08026 0ff44 0ff26 08100 08002 08000 x 1 y 1 pd16664 pd16664 pd16664 pd16664 pd16667 pd16667 m m m m m m specified by a 7 to a 0 specified by a 16 to a 8 160-output mode no. 0 00026 00100 00024 00126 07e00 07f02 07e26 07f26 no. 1 0fe00 0ff00 08026 08126 0ff02 0fe26 0ff26 no. 2 00028 00128 0004e 0014e 07e28 07f28 07e4e 07f4e no. 3 08028 08128 0804e 0814e 0fe28 0ff28 0fe4e 0ff4e y 160 y 160 y 1 y 1 y 160 y 160 y 1 x 128 x 1 x 128 0004c 0002a 07f4c 07f2a 00002 00000 07f00 07f24 08024 0ff24 0804c 0802a 0ff4c 0ff2a 08100 08002 08000 x 1 pd16667 pd16667 y 1 pd16664 pd16664 pd16664 pd16664 m m m m m m specified by a 16 to a 8 specified by a 7 to a 0 ?
data sheet s13780ej1v0ds00 20 m m m m pd16664 184-output mode no. 0 0002c 00100 0002a 0012c 07e00 07f02 07e2c 07f2c no. 1 0fe00 0ff00 0802c 0812c 0ff02 0fe2c 0ff2c no. 2 0002e 0012e 0005a 0015a 07e2e 07f2e 07e5a 07f5a no. 3 0802e 0812e 0805a 0815a 0fe2e 0ff2e 0fe5a 0ff5a y 184 y 184 y 1 y 1 y 184 y 184 y 1 x 128 x 1 x 128 00058 00030 07f58 07f30 00002 00000 07f00 07f2a 0802a 0ff2a 08058 08030 0ff58 0ff30 08100 08002 08000 x 1 y 1 pd16664 pd16664 pd16664 pd16664 pd16667 pd16667 m m m m m m specified by a 7 to a 0 specified by a 16 to a 18 208-output mode no. 0 00032 00100 00030 00132 07e00 07f02 07e32 07f32 no. 1 0fe00 0ff00 08032 08132 0ff02 0fe32 0ff32 no. 2 00034 00134 00066 00166 07e34 07f34 07e66 07f66 no. 3 08034 08134 08066 08166 0fe34 0ff34 0fe66 0ff66 y 208 y 208 y 1 y 1 y 208 y 208 y 1 x 128 x 1 x 128 00064 00036 07f64 07f36 00002 00000 07f00 07f30 08030 0ff30 08064 08036 0ff64 0ff36 08100 08002 08000 x 1 y 1 pd16664 pd16664 pd16664 pd16664 pd16667 pd16667 m m m m m m specified by a 7 to a 0 specified by a 16 to a 8
data sheet s13780ej1v0ds00 21 m m m m pd16664 vertically long address dir = h, dmode = h 144-output mode no. 0 00000 00100 00022 00122 07e00 07f00 07e22 07f22 no. 1 08000 08100 08022 08122 0fe00 0ff00 0fe22 0ff22 no. 2 00024 00124 00046 00146 07e24 07f24 07e46 08046 no. 3 08024 08124 07f46 08146 0fe24 0ff24 0fe46 0ff46 0ff02 0ff20 0ff26 0ff44 08044 08026 07f26 07f44 07f20 08020 08002 07f02 00002 00020 00026 00044 pd16667 pd16667 x 128 x 1 x 128 x 1 y 1 y 144 y 1 y 144 pd16664 pd16664 pd16664 pd16664 y 144 y 1 y 144 y 1 m m m m m m specified by a 16 to a 8 specified by a 7 to a 0 ?
data sheet s13780ej1v0ds00 22 m m m m pd16664 160-output mode no. 0 00000 00100 00026 00126 07e00 07f00 07e26 07f26 no. 1 08000 08100 08026 08126 0fe00 0ff00 0fe26 0ff26 no. 2 00028 00128 0004e 0014e 07e28 07f28 07e4e 0804e no. 3 08028 08128 07f4e 0814e 0fe28 0ff28 0fe4e 0ff4e 0ff02 0ff24 0ff2a 0ff4c 0804c 0802a 07f2a 07f4c 07f24 08024 08002 07f02 00002 00024 0002a 0004c pd16667 pd16667 x 128 x 1 x 128 x 1 y 1 y 160 y 1 y 160 pd16664 pd16664 pd16664 pd16664 y 160 y 1 y 160 y 1 m m m m m m specified by a 16 to a 8 specified by a 7 to a 0
data sheet s13780ej1v0ds00 23 m m m m pd16664 184-output mode no. 0 00000 00100 0002c 0012c 07e00 07f00 07e2c 07f2c no. 1 08000 08100 0802c 0812c 0fe00 0ff00 0fe2c 0ff2c no. 2 0002e 0012e 0005a 0015a 07e2e 07f2e 07e5a 0805a no. 3 0802e 0812e 07f5a 0815a 0fe2e 0ff2e 0fe5a 0ff5a 0ff02 0ff2a 0ff30 0ff58 08058 08030 07f30 07f58 07f2a 0802a 08002 07f02 00002 0002a 00030 00058 pd16667 pd16667 x 128 x 1 x 128 x 1 y 1 y 184 y 1 y 184 pd16664 pd16664 pd16664 pd16664 y 184 y 1 y 184 y 1 m m m m m m specified by a 16 to a 8 specified by a 7 to a 0
data sheet s13780ej1v0ds00 24 m m m m pd16664 208-output mode no. 0 00000 00100 00032 00132 07e00 07f00 07e32 07f32 no. 1 08000 08100 08032 08132 0fe00 0ff00 0fe32 0ff32 no. 2 00034 00134 00066 00166 07e34 07f34 07e66 08066 no. 3 08034 08134 07f66 08166 0fe34 0ff34 0fe66 0ff66 0ff02 0ff30 0ff36 0ff64 08064 08036 07f36 07f64 07f30 08030 08002 07f02 00002 00030 00036 00064 pd16667 pd16667 x 128 x 1 x 128 x 1 y 1 y 208 y 1 y 208 pd16664 pd16664 pd16664 pd16664 y 208 y 1 y 208 y 1 m m m m m m specified by a 16 to a 8 specified by a 7 to a 0
data sheet s13780ej1v0ds00 25 m m m m pd16664 12. cpu interface 12.1 function of rdy(ready) pin the internal ram is a single-port ram. the cpu is kept waiting so that access from the cpu does not conflict with reading by the driver. (1) timing hi-z hi-z a 0 to a 16 ,/ube /cs /oe,/we rdy wait ready wait (2) connection of rdy pin the rdy pin uses a three-state buffer. the rdy pin should be connected to an external pull-up resistor. if more than one lsi are used, the rdy pins of each lsi are wired together. rdy rdy cpu v cc2 column driver column driver pull-up resistor ready input
data sheet s13780ej1v0ds00 26 m m m m pd16664 12.2 access timing (1) display data read timing a 16 to a 0 d 15 to d 0 /ube /cs /oe rdy hi-z hi-z hi-z hi-z dout (2) display data write timing a 16 to a 0 d 15 to d 0 /ube /cs /we rdy hi-z hi-z din (3) gray level palette data write timing a 16 to a 0 d 15 to d 0 /ube /cs /we rdy hi-z din
data sheet s13780ej1v0ds00 27 m m m m pd16664 13. initializational function the m pd16664 has two types of initialization functions. 13.1 initialization by /reset /reset is the pin that is used to forcibly initialize the internal status of the ic from outside the ic. in the case of /reset = l, the internal status of ic is as follows: oscillator stopped. liquid crystal timing generation circuit initialized. internal timing generation circuit initialized. self-diagnostic circuit initialized. at power-on, be sure to perform initialization using /reset. 13.2 initialization by /refrh /refrh is the pin that is used when the internal self-diagnostic circuit initializes the internal status of ic in cases when the timing of the column drivers deviate due to external noise, etc. in the case of /refrh = l, the internal status of ic is as follows: oscillator stopped. liquid crystal timing generation circuit initialized. internal timing generation circuit initialized. 14. display-off function when /doff = l, all column driver outputs yn become v 1 level, and because the /dout output becomes l at the same time, the row driver will be /doff = l and all row driver outputs xn will also be v 1 level. therefore, the display is forcibly turned off without regard to the display data. at power-on, be sure to make /doff = l until each power supply is stabilized. remark /doff is the input pin of the row driver.
data sheet s13780ej1v0ds00 28 m m m m pd16664 15. liquid crystal timing generation circuit if the master mode is set by making ms high, /frm and stb are generated at timing with a duty factor (1/128,1/160). driver drive voltage select signals l1 and l2 are generated for a row driver. /frm is generated two times in 1 frame. when a duty rate is 1/160, stb is generated 81 times in 1/2 frame and 162 times in 1 frame. when a duty rate is 1/128, stb is generated 65 times in 1/2 frame and 130 times in 1 frame. ? /frm and stb signal generation osc1 pulse stb /frm 12 3 4 stb 2 1 81 80 3 2 1 81 80 3 2 1 81 /frm stb 2 1 65 64 3 2 1 65 64 3 2 1 65 frame frame duty 1/160 duty 1/128 ? l1 and l2 signal generation stb 1234123412341234 l1 1111111100000000 l2 1010010101011010
data sheet s13780ej1v0ds00 29 m m m m pd16664 16. self-diagnosis function this function checks whether the timing of each column driver is different from that of the others due to external noise. a slave chip compares internally generated l1 and l2 with l1 and l2 of the master chip. if a discrepancy is found, a refresh signal is transmitted to all column drivers. on reception of the refresh signal, internal reset is effected, and timing is initialized. at this time, the display is turned off while /refrh = l for 4 frame cycles. discrepancy between l1 and l2 is monitored at the rising edge of /frm once in 1/2 frame. l1(master) l2(master) l1(slave) l2 (slave) /refrh discrepancy initialization initialization discrepancy block configuration (slave side) /reset /refrh l1 l2 self-diagnosis circuit internal l1 signal internal l2 signal internal reset
data sheet s13780ej1v0ds00 30 m m m m pd16664 17. system configuration example here is an example using a liquid crystal panel of 416 x 320 pixels, horizontally long by using four m pd16664s and two row drivers. ? the lsi no. of each column driver is set by the pl0 and pl1 pins. ? the dir pin of each column driver is set to low. ? the cmode0, cmode1 and dmode pins of each column driver are set to low. ? one of the column drivers is set as a master and the others are set as slaves. the master column driver supplies signals to the slave column drivers and row drivers. ? a resistor for oscillation is connected to the osc1 and osc2 pins of the master. these pins of the slaves are left open. ? all the signals from the system (d 0 to d 15 , a 0 to a 16 , /cs, /oe, /we, /ube, rdy, /reset, and /doff) are connected in parallel with the column drivers. a pull-up resistor is connected to the rdy pin. ? the test pin is used to test the lsi and is open or connected to gnd when the system is constructed. rdy /doff /reset d 0 to d 15 a 0 to a 16 control (/cs, /oe, /we, /ube) master no. 0 slave no. 2 slave no. 1 slave no. 3 osc1 osc2 160 160 y 1 y 1 y 208 y 208 y 1 y 208 y 1 y 208 row driver pulse stb /frm /refrh /dout,/doff' l1 l2 row driver scan direction scan direction v cc2
data sheet s13780ej1v0ds00 31 m m m m pd16664 18. chip set power-up sequence it is recommended to apply power in the following sequence: v cc2 ? v cc1 ? input ? v dd , v ee ? v 1 , v 2 be sure to apply lcd drive voltages v 1 , v 2 in the end. v cc2 v cc1 v dd v ee v 1 v 2 /reset off off off off off off 0 v 0 v on on on on on on 4.5 v v cc2 v cc2 0.3 v cc2 100 ns or longer cpu interface (a 0 to a 16 ,/cs,/oe, /we,/ube,d 0 to d 15 ) 0 v v cc2 0.3 v cc2 /doff 0 s or more note note 0 s or more 0 s or more 0 s or more note v dd and v ee do not have to be turned on at the same time. caution turn off power to the chip set in the sequence reverse to the above.
data sheet s13780ej1v0ds00 32 m m m m pd16664 19. example of connecting of internal schottky barrier diode of module to reinforce power supply protection v dd note v cc1 v 2 v 1 v 0 v ss v ee note diodes enclosed in a dotted line in the above figure must be connected when v 0 is other than 0 v (gnd). note v dd and v ee are lcd power supply lines of row driver. remark use schottky barrier diodes with v f = 0.5 v or less.
data sheet s13780ej1v0ds00 33 m m m m pd16664 20. electrical specifications absolute maximum ratings (t a = 25c) parameter symbol ratings unit supply voltage (1) note1 v cc1 C0.5 to +6.5 v supply voltage (2) note2 v cc2 C0.5 to +4.5 v input/output voltage (1) note1 v i/o1 C0.5 to v cc1 + 0.5 v input/output voltage (2) note2 v i/o2 C0.5 to v cc2 + 0.5 v input/output voltage (3) note3 v i/o3 C0.5 to v cc1 + 0.5 v operating ambient temperature t a C20 to +70 c storage temperature t stg C40 to +125 c notes 1. v cc1 signals (/frm, stb, /dout, l1, l2, pulse) 2. v cc2 signals (ms, dir, pl0 and pl1, a 0 to a 16 , /cs, /oe, /we, /ube, rdy, d 0 to d 15 , /reset, osc1, osc2, /doff, test, bmode, /refrh, cmode0, cmode1, dmode) 3. liquid crystal power (v 0 , v 1 , v 2 , y 1 to y 208 ) caution if the absolute maximum rating of even one of the above parameters is exceeded even momentarily, the quality of the product may be degraded. absolute maximum ratings, therefore, specify the values exceeding which the product may be physically damaged. be sure to use the product within the range of the absolute maximum ratings. recommended operating conditions (t a = C20 to +70c, v 0 = 0 v) parameter symbol min. typ. max. unit supply voltage (1) v cc1 4.5 5.0 5.5 v supply voltage (2) v cc2 2.4 3.6 v input voltage (1) note1 v i1 0v cc1 v input voltage (2) note2 v i2 0v cc2 v v 1 input voltage v 1 v 0 v 2 v v 2 input voltage v 2 v 1 v cc1 v external resistor for osc r osc 75 270 k w notes 1. v cc1 signals (/frm, stb, l1, l2, pulse) 2. v cc2 signals (ms, dir, pl0 and pl1, a 0 to a 16 , /cs, /oe, /we, /ube, rdy, d 0 to d 15 , /reset, osc1, osc2, /doff, test, bmode, /refrh, cmode0, cmode1, dmode)
data sheet s13780ej1v0ds00 34 m m m m pd16664 dc characteristics (unless otherwise specified, v cc1 = 4.5 to 5.5 v, v 0 = 0 v, v 1 = 1.4 to 2.0 v, v 2 = 2.8 to 4.0 v, t a = C20 to +70c) { v cc2 = 3.0 to 3.6 v parameter symbol conditions min. typ. max. unit high-level input voltage (1), v cc1 note1 v ih1 0.7 v cc1 v low-level input voltage (1), v cc1 note1 v il1 0.3 v cc1 v high-level input voltage (2), v cc2 note2 v ih2 0.7 v cc2 v low-level input voltage (2), v cc2 note2 v il2 0.3 v cc2 v high-level input voltage (2), v cc2 note3 v ih3 0.8 v cc2 v low-level input voltage (2), v cc2 note3 v il3 0.2 v cc2 v high-level output voltage (1), v cc1 note4 v oh1 i oh = C1 ma v cc1 C 0.4 v low-level output voltage (1), v cc1 note4 v ol1 i ol = 2 ma 0.4 v high-level output voltage (2), v cc1 note1 v oh2 i oh = C2 ma v cc1 C 0.4 v low-level output voltage (2), v cc1 note1,3 v ol2 i ol = 4 ma 0.4 v high-level output voltage (3), v cc2 note5 v oh3 i oh = C1 ma v cc2 C 0.4 v low-level output voltage (3), v cc2 note5 v ol3 i ol = 2 ma 0.4 v input leakage current (1) i i1 other than test pin, v 1 = v cc2 or gnd 10 m a input leakage current (2) i i2 pull down (test pin), v 1 = v cc2 10 40 100 m a display operating current consumption (1) note6 i mas1 master, v cc1 80 m a display operating current consumption (2) note6 i mas2 master, v cc2 200 m a display operating current consumption (3) note6 i slv1 slave, v cc1 50 m a display operating current consumption (4) note6 i slv2 slave, v cc2 130 m a liquid crystal driver output on resistance note7 r on 12k w notes 1. v cc1 signal (/frm, stb, l1, l2, pulse) 2. v cc2 signal (ms, dir, pl0 and pl1, a 0 to a 16 , /cs, /oe, /we, /ube, rdy, d 0 to d 15 , /reset, /doff, test, bmode, cmode0, cmode1, dmode) 3. /refrh pin 4. /dout pin 5. d 0 to d 15 , rdy, osc2 pins 6. frame frequency: 70 hz, output: no load, not accessed by cpu (d 0 to d 15 , a 0 to a 16 , /ube = gnd, /cs, /oe, /we = v cc2 ) 7. resistance between y and v pins (any of v 0 , v 1 , and v 2 ) when a load current (i on = 100 m a) flows through one pin of y 1 to y 208 . ? ? ? ?
data sheet s13780ej1v0ds00 35 m m m m pd16664 { v cc2 = 2.4 to 3.0 v parameter symbol conditions min. typ. max. unit high-level input voltage (1), v cc1 note1 v ih1 0.7 v cc1 v low-level input voltage (1), v cc1 note1 v il1 0.3 v cc1 v high-level input voltage (2), v cc2 note2 v ih2 0.7 v cc2 v low-level input voltage (2), v cc2 note2 v il2 0.3 v cc2 v high-level input voltage (2), v cc2 note3 v ih3 0.8 v cc2 v low-level input voltage (2), v cc2 note3 v il3 0.2 v cc2 v high-level output voltage (1), v cc1 note4 v oh1 i oh = C1 ma v cc1 C 0.4 v low-level output voltage (1), v cc1 note4 v ol1 i ol = 2 ma 0.4 v high-level output voltage (2), v cc1 note1 v oh2 i oh = C2 ma v cc1 C 0.4 v low-level output voltage (2), v cc1 note1,3 v ol2 i ol = 4 ma 0.4 v high-level output voltage (3), v cc2 note5 v oh3 i oh = C1 ma v cc2 C 0.4 v low-level output voltage (3), v cc2 note5 v ol3 i ol = 2 ma 0.4 v input leakage current (1) i i1 other than test pin, v 1 = v cc2 or gnd 10 m a input leakage current (2) i i2 pull down (test pin), v 1 = v cc2 10 40 100 m a display operating current consumption (1) note6 i mas1 master, v cc1 100 m a display operating current consumption (2) note6 i mas2 master, v cc2 150 m a display operating current consumption (3) note6 i slv1 slave, v cc1 60 m a display operating current consumption (4) note6 i slv2 slave, v cc2 100 m a liquid crystal driver output on resistance note7 r on 1.2 2.4 k w notes 1. v cc1 signal (/frm, stb, l1, l2, pulse) 2. v cc2 signal (ms, dir, pl0 and pl1, a 0 to a 16 , /cs, /oe, /we, /ube, rdy, d 0 to d 15 , /reset, /doff, test, bmode, cmode0, cmode1, dmode) 3. /refrh pin 4. /dout pin 5. d 0 to d 15 , rdy, osc2 pins 6. frame frequency: 70 hz, output: no load, not accessed by cpu (d 0 to d 15 , a 0 to a 16 , /ube = gnd, /cs, /oe, /we = v cc2 ) 7. resistance between y and v pins (any of v 0 , v 1 , and v 2 ) when a load current (i on = 100 m a) flows through one pin of y 1 to y 208 . ? ? ? ?
data sheet s13780ej1v0ds00 36 m m m m pd16664 ac characteristics 1 display data transfer timing (1) master mode (unless otherwise specified, v cc1 = 4.5 to 5.5 v, v cc2 = 2.4 to 3.6 v, v 0 = 0 v, v 1 = 1.4 to 2.0 v, v 2 = 2.8 to 4.0 v, t a = C20 to +70c, frame frequency: 70 hz (f osc = 90.72 khz at 1/160 duty, 72.8 khz at 1/128 duty), output load: 100 pf) parameter symbol conditions min. typ. max. unit 1/160 duty 87 8/f osc m s stb clock cycle time t cyc 1/128 duty 108 8/f osc m s 1/160 duty 43 4/f osc m s stb high-level width t cwh 1/128 duty 54 4/f osc m s 1/160 duty 43 4/f osc m s stb low-level width t cwl 1/128 duty 54 4/f osc m s stb rise time t r 100 ns stb fall time t f 100 ns stb - /frm delay time t psf 20 m s /frm - stb delay time t pfs 20 m s stb (output) /frm (output) t f t r t cwl t psf t psf t pfs t pfs t cwh t cyc 0.9 v cc1 0.1 v cc1 0.9 v cc1 0.1 v cc1
data sheet s13780ej1v0ds00 37 m m m m pd16664 (2) slave mode (unless otherwise specified, v cc1 = 4.5 to 5.5 v, v cc2 = 2.4 to 3.6 v, v 0 = 0 v, v 1 = 1.4 to 2.0 v, v 2 = 2.8 to 4.0 v, t a = C20 to +70 c) parameter symbol conditions min. typ. max. unit stb clock cycle time t cyc 10 m s stb high-level width t cwh 4 m s stb low-level width t cwl 4 m s stb rise time t r 150 ns stb fall time t f 150 ns /frm setup time t sfr 1 m s /frm hold time t hfr 1 m s stb (input) /frm (input) t f t r t cwl t sfr t sfr t hfr t hfr t cwh t cyc 0.7 v cc1 0.3 v cc1 0.7 v cc1 0.3 v cc1
data sheet s13780ej1v0ds00 38 m m m m pd16664 (3) parameters common to master/slave (unless otherwise specified, v cc1 = 4.5 to 5.5 v, v 0 = 0 v, v 1 = 1.4 to 2.0 v, v 2 = 2.8 to 4.0 v, t a = C20 to +70c) { v cc2 = 3.0 to 3.6 v parameter symbol conditions min. typ. max. unit output delay time (l1, l2) t dout1 no output load 50 100 ns output delay time (y 1 to y 208 )t dout2 no output load 90 150 ns { v cc2 = 2.4 to 3.0 v parameter symbol conditions min. typ. max. unit output delay time (l1, l2) t dout1 no output load 120 ns output delay time (y 1 to y 208 )t dout2 no output load 180 ns stb (output) y 1 to y 208 0.9 v 2 0.9 v 2 0.9 v cc1 0.9 v cc1 t dout2 t dout2 t dout1 t dout1 0.1 v 2 0.1 v 2 l1, l2
data sheet s13780ej1v0ds00 39 m m m m pd16664 ac characteristics 2 drawing access timing (unless otherwise specified, v cc1 = 4.5 to 5.5 v, v 0 = 0 v, v 1 = 1.4 to 2.0 v, v 2 = 2.8 to 4.0 v, t a = C20 to +70c, t r = t f = 5 ns) { v cc2 = 3.0 to 3.6 v parameter symbol conditions min. typ. max. unit /oe,/we recovery time t ry 30 ns address setup time t as 10 ns address hold time t ah 20 ns rdy output delay time t ryr c l = 15 pf 30 ns rdy float time note 1 t ryz 30 ns wait status time note 2 t ryw 35 ns ready status time (without conflict) note 2 t ryf1 60 100 ns ready status time (with conflict) note 2 t ryf2 650 1200 ns data access time (read cycle) note 3 t acs 100 ns data float time (read cycle) note 1 t hz 40 ns /cs - /oe time (read cycle) t csoe 10 ns /oe - /cs time (read cycle) t oecs 20 ns write pulse width 1 (write cycle 1) note 2 t wp1 50 ns write pulse width 2 (write cycle 2) note 2 t wp2 50 ns data setup time (write cycles 1, 2) t dw 20 ns data hold time (write cycles 1, 2) t dh 20 ns /cs - /we time (write cycles 1, 2) t cswe 10 ns /we - /cs time (write cycles 1, 2) t wecs 20 ns reset pulse width t wres 100 ns rdy - /oe time t rdoe note 4 C rdy - /we time t rdwe note 4 C notes 1. load circuit 1.0 k w 1.8 k w v cc2 5 pf
data sheet s13780ej1v0ds00 40 m m m m pd16664 2. load circuit 1.0 k w 1.8 k w v cc2 60 pf 3. load circuit 1.0 k w 1.8 k w v cc2 100 pf 4. the display may be affected if the time from the rising of rdy to /oe or /we is too long. it is recommended that t rdoe and t rdwe be 1000 ns or less.
data sheet s13780ej1v0ds00 41 m m m m pd16664 { v cc2 = 2.4 to 3.0 v parameter symbol conditions min. typ. max. unit /oe,/we recovery time t ry 40 ns address setup time t as 20 ns address hold time t ah 30 ns rdy output delay time t ryr c l = 15 pf 40 ns rdy float time note 1 t ryz 40 ns wait status time note 2 t ryw 50 ns ready status time (without conflict) note 2 t ryf1 120 ns ready status time (with conflict) note 2 t ryf2 1600 ns data access time (read cycle) note 3 t acs 120 ns data float time (read cycle) note 1 t hz 50 ns /cs - /oe time (read cycle) t csoe 20 ns /oe - /cs time (read cycle) t oecs 30 ns write pulse width 1 (write cycle 1) note 2 t wp1 60 ns write pulse width 2 (write cycle 2) note 2 t wp2 60 ns data setup time (write cycles 1, 2) t dw 30 ns data hold time (write cycles 1, 2) t dh 30 ns /cs - /we time (write cycles 1, 2) t cswe 20 ns /we - /cs time (write cycles 1, 2) t wecs 30 ns reset pulse width t wres 120 ns rdy - /oe time t rdoe note 4 C rdy - /we time t rdwe note 4 C notes 1. load circuit 1.0 k w 1.8 k w v cc2 5 pf
data sheet s13780ej1v0ds00 42 m m m m pd16664 2. load circuit 1.0 k w 1.8 k w v cc2 60 pf 3. load circuit 1.0 k w 1.8 k w v cc2 100 pf 4. the display may be affected if the time from the rising of rdy to /oe or /we is too long. it is recommended that t rdoe and t rdwe be 1000 ns or less.
data sheet s13780ej1v0ds00 43 m m m m pd16664 /oe,/we recovery time /oe,/we t ry 0.7 v cc2 0.3 v cc2 read cycle a 16 to a 0 /ube /cs /oe rdy d 15 to d 0 hi-z t ryr t ryf t ryw t hz t acs t csoe t as t ah t rdoe t oecs 0.1 v cc2 0.7 v cc2 0.7 v cc2 0.3 v cc2 0.3 v cc2 0.9 v cc2 0.1 v cc2 0.3 v cc2 0.1 v cc2 t ryz 0.7 v cc2 0.3 v cc2 0.9 v cc2 out
data sheet s13780ej1v0ds00 44 m m m m pd16664 write cycle 1 (on writing display data) a 16 to a 0 /ube /cs /we rdy d 15 to d 0 hi-z t ryr t ryf t dh t dw t wp1 t cswe t as t ah t rdwe t wecs 0.1 v cc2 0.7 v cc2 0.7 v cc2 0.3 v cc2 0.3 v cc2 0.7 v cc2 0.3 v cc2 0.3 v cc2 t ryz 0.1 v cc2 0.7 v cc2 0.3 v cc2 t ryw 0.9 v cc2 in write cycle 2 (on writing gray level palette) a 16 to a 0 /ube /cs /we rdy d 15 to d 0 hi-z t wp2 t dh t dw t cswe t as t ah t wecs 0.7 v cc2 0.7 v cc2 0.3 v cc2 0.3 v cc2 0.7 v cc2 0.3 v cc2 0.3 v cc2 in
data sheet s13780ej1v0ds00 45 m m m m pd16664 reset pulse width /reset 0.3 v cc2 t wres ac characteristics 3 cr oscillation { v cc2 = 2.4 to 3.6 v, t a = C20 to +70 c, 1/160 duty parameter symbol conditions min. typ. max. unit oscillation frequency f osc external resistor: 130 k w 80 95 110 khz frame frequency C external resistor: 130 k w 61.7 73.3 84.9 hz { v cc2 = 2.4 to 3.6 v, t a = C20 to +70 c, 1/128 duty parameter symbol conditions min. typ. max. unit oscillation frequency f osc external resistor: 160 k w 64 76 88 khz frame frequency C external resistor: 160 k w 61.5 73.1 84.6 hz ? ?
data sheet s13780ej1v0ds00 46 m m m m pd16664 21. relation between oscillation frequency, frame frequency, and stb frequency the relation between the oscillation frequency, frame frequency, and stb frequency is as follows: 1/160 duty frame frequency = 4 2 162 1 oscillation frequency stb frequency = 4 2 1 oscillation frequency 1/128 duty frame frequency = 4 2 130 1 oscillation frequency stb frequency = 4 2 1 oscillation frequency
data sheet s13780ej1v0ds00 47 m m m m pd16664 22. package drawings standard tcp package drawing ( m m m m pd16664n-001) (1/3) material polyimide upilex-s t = 75 m m adhesive epoxy t = 12 m m copper electrolysis cu t = 18 m m plating sn t = 0.15 m m min solder resist epoxy t = 25 m m this products is single side flex type. this figure is shown by copper side over polymide. all tolerances unless otherwise specified 0.05 mm. corner radius is 0.30 mm max. 13 sprocket holes (61.75 mm) for 1 pattern.
data sheet s13780ej1v0ds00 48 m m m m pd16664 standard tcp package drawing ( m m m m pd16664n-001) (2/3) eiaj test pad details from p.c. from p.c. alignment details from p.c. from p.c. tcp tape winding direction output lead tape pull-up direction the cu pattern side is the underside of the tape wind-up direction
data sheet s13780ej1v0ds00 49 m m m m pd16664 standard tcp package drawing ( m m m m pd16664n-001) (3/3) pin configuration dummy dummy y 208 y 207 y 206 y 205 y 204 y 203 y 202 y 201 y 200 y 199 dummy v 0 v 1 v 2 v cc1 gnd v cc2 gnd a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 a 9 a 10 a 11 a 12 a 13 a 14 a 15 a 16 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 8 d 9 d 10 d 11 d 12 d 13 d 14 d 15 v cc2 osc1 osc2 gnd dir pl0 pl1 /refrh /reset /ube /cs /oe /we rdy /doff test bmode cmode0 cmode1 dmode ms v cc2 gnd pulse /frm stb /dout l2 l1 v cc1 gnd v 2 v 1 v 0 dummy no.1 no.2 no.3 no.4 no.5 no.6 no.7 no.8 no.9 no.10 no.11 no.12 no.13 no.14 no.15 no.16 no.17 no.18 no.19 no.20 no.21 no.22 no.23 no.24 no.25 no.26 no.27 no.28 no.29 no.30 no.31 no.32 no.33 no.34 no.35 no.36 no.37 no.38 no.39 no.40 no.41 no.42 no.43 no.44 no.45 no.46 no.47 no.48 no.49 no.50 no.51 no.52 no.53 no.54 no.55 no.56 no.57 no.58 no.59 no.60 no.61 no.62 no.63 no.64 no.65 no.66 no.67 no.68 no.69 no.70 no.71 no.72 no.73 no.74 no.75 no.76 no.1 no.2 no.3 no.4 no.5 no.6 no.7 no.8 no.9 no.10 no.11 no.12 y 10 y 9 y 8 y 7 y 6 y 5 y 4 y 3 y 2 y 1 dummy dummy no.201 no.202 no.203 no.204 no.205 no.206 no.207 no.208 no.209 no.210 no.211 no.212
data sheet s13780ej1v0ds00 50 m m m m pd16664 [memo]
data sheet s13780ej1v0ds00 51 m m m m pd16664 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function.
m m m m pd16664 reference documents nec semiconductor device reliability/quality control system (c10983e) quality grades to necs semiconductor devices (c11531e) the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. nec corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. m7 98. 8

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